View AD9228-65EB_824938.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

quad, 12-bit, 40/65 msps serial lvds 1.8 v a/d converter ad9228 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features four adcs integrated into 1 package 119 mw adc power per channel at 65 msps snr = 70 db (to nyquist) excellent linearity dnl = 0.3 lsb (typical) inl = 0.4 lsb (typical) serial lvds (ansi-644, default) low power reduced signal option, ieee 1596.3 similar data and frame clock outputs 315 mhz full power analog bandwidth 2 v p-p input voltage range 1.8 v supply operation serial port control full-chip and individual-channel power-down modes flexible bit orientation built-in and custom digital test pattern generation programmable clock and data alignment programmable output resolution standby mode applications medical imaging and nondestructive ultrasound portable ultrasound and digital beam forming systems quadrature radio receivers diversity radio receivers tape drives optical networking test equipment general description the ad9228 is a quad, 12-bit, 40/65 msps analog-to-digital converter (adc) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 65 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl-/ cmos-/lvds-compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock (dco) for functional block diagram serial lvds ref select + ? ad9228 agnd vin?a vin+a vin?b vin+b vin?d vin+d vin?c vin+c sense vref a v dd drvdd 12 12 12 12 pdwn reft refb d?a d+a d?b d+b d?d d+d d?c d+c fco? fco+ dco+ dco? clk+ drgnd clk? serial port interface csb sclk/dtp sdio/odm rbias serial lvds serial lvds serial lvds pipeline adc pipeline adc pipeline adc pipeline adc data rate multiplier 0.5v 0 5727-001 figure 1. capturing data on the output and a frame clock (fco) for signaling a new output byte are provided. individual channel power-down is supported and typically consumes less than 2 mw when all channels are disabled. the adc contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. the available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (spi?). the ad9228 is available in a pb-free, 48-lead lfcsp package. it is specified over the industrial temperature range of ?40c to +85c. product highlights 1. small footprint. four adcs are contained in a small, space- saving package; low power of 119 mw/channel at 65 msps. 2. ease of use. a data clock output (dco) is provided that operates up to 390 mhz and supports double data rate operation (ddr). 3. user flexibility. serial port interface (spi) control offers a wide range of flexible features to meet specific system requirements. 4. pin-compatible family. this includes the ad9287 (8-bit), ad9219 (10-bit), and ad9259 (14-bit).
ad9228 rev. 0 | page 2 of 52 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac specifications.......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing diagrams.............................................................................. 7 absolute maximum ratings............................................................ 9 thermal impedance ..................................................................... 9 esd caution.................................................................................. 9 pin configuration and function descriptions........................... 10 equivalent circuits ......................................................................... 12 typical performance characteristics ........................................... 14 theory of operation ...................................................................... 19 analog input considerations ................................................... 19 clock input considerations...................................................... 21 serial port interface (spi).............................................................. 29 hardware interface..................................................................... 29 memory map .................................................................................. 31 reading the memory map table.............................................. 31 reserved locations .................................................................... 31 default values ............................................................................. 31 logic levels................................................................................. 31 evaluation board ............................................................................ 35 power supplies ............................................................................ 35 input signals................................................................................ 35 output signals ............................................................................ 35 default operation and jumper selection settings................. 36 alternative analog input drive configuration...................... 37 outline dimensions ....................................................................... 51 ordering guide .......................................................................... 51 revision history 4/06revision 0: initial version
ad9228 rev. 0 | page 3 of 52 specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 1. ad9228-40 ad9228-65 parameter 1 temperature min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full guaranteed guaranteed offset error full 1 8 1 8 mv offset matching full 2 8 2 8 mv gain error full 0.4 1.2 2 3.5 % fs gain matching full 0.3 0.7 0.3 0.7 % fs differential nonlinearity (dnl) full 0.25 0.5 0.3 0.65 lsb integral nonlinearity (inl) full 0.4 1 0.4 1 lsb temperature drift offset error full 2 2 ppm/c gain error full 17 17 ppm/c reference voltage (1 v mode) full 21 21 ppm/c reference output voltage error (vref = 1 v) full 2 30 2 30 mv load regulation @ 1.0 ma (vref = 1 v) full 3 3 mv input resistance full 6 6 k analog inputs differential input voltage range (vref = 1 v) full 2 2 v p-p common-mode voltage full avdd/2 avdd/2 v differential input capacitance full 7 7 pf analog bandwidth, full power full 315 315 mhz power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v iavdd full 155 170 232 245 ma idrvdd full 31 34 34 38 ma total power dissipation (including output drivers) full 335 367 478 510 mw power-down dissipation full 2 5.8 2 5.8 mw standby dissipation 2 full 72 72 mw crosstalk full ?100 ?100 db crosstalk (overrange condition) 3 full ?100 ?100 db 1 see the an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions and how these tests were completed. 2 can be controlled via spi. 3 overrange condition is specific with 6 db of the full-scale input range.
ad9228 rev. 0 | page 4 of 52 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 2. ad9228-40 ad9228-65 parameter 1 temperature min typ max min typ max unit signal-to-noise ratio (snr) f in = 2.4 mhz full 70.5 70.2 db f in = 19.7 mhz full 68.5 70.2 70.0 db f in = 35 mhz full 70.2 68.5 70.0 db f in = 70 mhz full 70.0 69.5 db signal-to-noise and distortion ratio (sinad) f in = 2.4 mhz full 70.3 70.0 db f in = 19.7 mhz full 68.0 69.8 70.0 db f in = 35 mhz full 69.7 68.0 69.8 db f in = 70 mhz full 69.5 69.0 db effective number of bits (enob) f in = 2.4 mhz full 11.4 11.37 bits f in = 19.7 mhz full 11.1 11.37 11.33 bits f in = 35 mhz full 11.37 11.1 11.33 bits f in = 70 mhz full 11.33 11.25 bits spurious-free dynamic range (sfdr) f in = 2.4 mhz full 85 85 dbc f in = 19.7 mhz full 72 82 85 dbc f in = 35 mhz full 80 73 84 dbc f in = 70 mhz full 80 74 dbc worst harmonic (second or third) f in = 2.4 mhz full ?85 ?85 dbc f in = 19.7 mhz full ?82 ?72 ?85 dbc f in = 35 mhz full ?80 ?84 ?73 dbc f in = 70 mhz full ?80 ?74 dbc worst other (excluding second or third) f in = 2.4 mhz full ?90 ?90 dbc f in = 19.7 mhz full ?90 ?80 ?90 dbc f in = 35 mhz full ?90 ?90 ?79 dbc f in = 70 mhz full ?90 ?88 dbc two-tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 15 mhz, f in2 = 16 mhz 25c 80.8 77.8 dbc f in1 = 70 mhz, f in2 = 71 mhz 25c 75.0 77.0 dbc 1 see the an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions and how these tests were completed.
ad9228 rev. 0 | page 5 of 52 digital specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 3. ad9228-40 ad9228-65 parameter 1 temperature min typ max min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl cmos/lvds/lvpecl differential input voltage 2 full 250 250 mv p-p input common-mode voltage full 1.2 1.2 v input resistance (differential) 25c 20 20 k input capacitance 25c 1.5 1.5 pf logic inputs (pdwn, sclk/dtp) logic 1 voltage full 1.2 3.6 1.2 3.6 v logic 0 voltage full 0 0.3 0.3 v input resistance 25c 30 30 k input capacitance 25c 0.5 0.5 pf logic input (csb) logic 1 voltage full 1.2 3.6 1.2 3.6 v logic 0 voltage full 0 0.3 0.3 v input resistance 25c 70 70 k input capacitance 25c 0.5 0.5 pf logic input (sdio/odm) logic 1 voltage full 1.2 drvdd + 0.3 1.2 drvdd + 0.3 v logic 0 voltage full 0 0.3 0 0.3 v input resistance 25c 30 30 k input capacitance 25c 2 2 pf logic output (sdio/odm) logic 1 voltage (i oh = 50 a) full 1.79 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 0.05 v digital outputs (d+, d?), (ansi-644) 1 logic compliance lvds lvds differential output voltage (v od ) full 247 454 247 454 mv output offset voltage (v os ) full 1.125 1.375 1.125 1.375 v output coding (default) offset binary offset binary digital outputs (d+, d?), (low power, reduced signal option) 1 logic compliance lvds lvds differential output voltage (v od ) full 150 250 150 250 mv output offset voltage (v os ) full 1.10 1.30 1.10 1.30 v output coding (default) offset binary offset binary 1 see the an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions and how these tests were completed. 2 this is specified for lvds and lvpecl only.
ad9228 rev. 0 | page 6 of 52 switching specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 4. ad9228-40 ad9228-65 parameter 1 temp min typ max min typ max unit clock 2 maximum clock rate full 40 65 msps minimum clock rate full 10 10 msps clock pulse width high (t eh ) full 12.5 7.7 ns clock pulse width low (t el ) full 12.5 7.7 ns output parameters 2 propagation delay (t pd ) full 2.0 2.7 3.5 2.0 2.7 3.5 ns rise time (t r ) (20% to 80%) full 300 300 ps fall time (t f ) (20% to 80%) full 300 300 ps fco propagation delay (t fco ) full 2.0 2.7 3.5 2.0 2.7 3.5 ns dco propagation delay (t cpd ) 3 full t fco + (t sample /24) t fco + (t sample /24) ns dco to data delay (t data ) 3 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps dco to fco delay (t frame ) 3 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps data to data skew (t data-max ? t data-min ) full 50 150 50 150 ps wake-up time (standby) 25c 600 600 ns wake-up time (power down) 25c 375 375 s pipeline latency full 10 10 clk cycles aperture aperture delay (t a ) 25c 500 500 ps aperture uncertainty (jitter) 25c <1 <1 ps rms out-of-range recovery time 25c 1 2 clk cycles 1 see the an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions and how these tests were completed. 2 can be adjusted via the spi interface. 3 t sample /24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
ad9228 rev. 0 | page 7 of 52 timing diagrams dco? dco+ d? d+ fco? fco+ ain clk? clk+ msb n ? 10 d10 n ? 10 d9 n ? 10 d8 n ? 10 d7 n ? 10 d6 n ? 10 d5 n ? 10 d4 n ? 10 d3 n ? 10 d2 n ? 10 d1 n ? 10 d0 n ? 10 d10 n ? 9 msb n ? 9 05727-039 n-1 n t data t frame t fco t pd t cpd t eh t a t el figure 2. 12-bit data serial stream (default) dco+ dco? clk+ fco+ fco? d? d+ clk? ain msb n?10 n-1 n d8 n?10 d7 n?10 d5 n?10 t data t frame t fco t pd d4 n?10 d6 n?10 d8 n?9 d7 n?9 d5 n?9 d6 n?9 d3 n?10 d1 n?10 msb n?9 d0 n?10 d2 n?10 t cpd t eh t a t el 05727-040 figure 3. 10-bit data serial stream
ad9228 rev. 0 | page 8 of 52 dco? dco+ d? d+ fco? fco+ ain clk? clk+ lsb (n ? 10) d0 (n ? 10) d1 (n ? 10) d2 (n ? 10) d3 (n ? 10) d4 (n ? 10) d5 (n ? 10) d6 (n ? 10) d7 (n ? 10) d8 (n ? 10) d9 (n ? 10) d10 (n ? 10) d0 (n ? 9) lsb (n ? 9) 05727-041 n-1 t a n t data t frame t fco t pd t cpd t eh t el figure 4. 12-bit data serial stream, lsb first
ad9228 rev. 0 | page 9 of 52 absolute maximum ratings table 5. parameter with respect to rating electrical avdd agnd ?0.3 v to +2.0 v drvdd drgnd ?0.3 v to +2.0 v agnd drgnd ?0.3 v to +0.3 v avdd drvdd ?2.0 v to +2.0 v digital outputs (d+, d?, dco+, dco?, fco+, fco?) drgnd ?0.3 v to +2.0 v clk+, clk? agnd ?0.3 v to +3.9 v vin+, vin? agnd ?0.3 v to +2.0 v sdio/odm agnd ?0.3 v to +2.0 v pdwn, sclk/dtp, csb agnd ?0.3 v to +3.9 v reft, refb, rbias agnd ?0.3 v to +2.0 v vref, sense agnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal impedance table 6. air flow velocity (m/s) ja 1 jb jc 0.0 24c/w 1.0 21c/w 12.6c/w 1.2c/w 2.5 19c/w 1 ja for a 4-layer pcb with solid ground plane (simulated). exposed pad soldered to pcb. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9228 rev. 0 | page 10 of 52 pin configuration and fu nction descriptions vin + a vin ? a avdd vin + d vin ? d drvdd drgnd clk+ clk? avdd drvdd drgnd avdd avdd csb sclk/dtp sdio/odm pdwn avdd avdd avdd avdd avdd avdd d + a d ? a d + b d ? b d + c d ? c d + d d ? d dco+ dco? fco+ fco? vin + b vin ? b vin + c vin ? c avdd reft refb vref sense avdd avdd rbias 11 12 10 9 8 7 6 5 4 3 2 1 25 24 26 27 28 29 30 31 32 33 34 35 36 22 21 23 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 05727-003 pin 1 indicator exposed paddle, pin 0 (bottom of package) ad9228 top view figure 5. 48-lead lfcsp top view table 7. pin function descriptions pin o. ame description 0 agnd analog ground (exposed paddle) 1, 2, 5, 6, 9, 10, 27, 32, 35, 36, 39, 45, 46 avdd 1.8 v analog supply 11, 26 drgnd digital output driver ground 12, 25 drvdd 1.8 v digital output driver supply 3 vin ? d adc d analog inputcomplement 4 vin + d adc d analog inputtrue 7 clk? input clockcomplement 8 clk+ input clocktrue 13 d ? d adc d complement digital output 14 d + d adc d true digital output 15 d ? c adc c complement digital output 16 d + c adc c true digital output 17 d ? b adc b complement digital output 18 d + b adc b true digital output 19 d ? a adc a complement digital output 20 d + a adc a true digital output 21 fco? frame clock outputcomplement 22 fco+ frame clock outputtrue 23 dco? data clock outputcomplement 24 dco+ data clock outputtrue 28 sclk/dtp serial clock/digital test pattern 29 sdio/odm serial data input- output/output driver mode 30 csb csb 31 pdwn power-down 33 vin + a adc a analog inputtrue 34 vin ? a adc a analog inputcomplement
ad9228 rev. 0 | page 11 of 52 pin no. name description 37 vin ? b adc b analog inputcomplement 38 vin + b adc b analog inputtrue 40 rbias external resistor sets the internal adc core bias current 41 sense reference mode selection 42 vref voltage reference input/output 43 refb differential reference (negative) 44 reft differential reference (positive) 47 vin + c adc c analog inputtrue 48 vin ? c adc c analog inputcomplement
ad9228 rev. 0 | page 12 of 52 equivalent circuits vin 05727-030 figure 6. equivalent analog input circuit 10 ? 10k ? 10k ? clk 10 ? 1.25v 05727-032 clk figure 7. equivalent clock input circuit 05727-035 s dio/odm 350 ? 30k ? figure 8. equivalent sdio/odm input circuit dr v dd drgnd d? d+ v v 05727 -005 v v figure 9. equivalent digital output circuit sclk/pdwn 0 5727-033 30k ? 1k ? figure 10. equivalent sclk/pdwn input circuit 100 ? rbias 05727-031 figure 11. equivale nt rbias circuit
ad9228 rev. 0 | page 13 of 52 csb 05727-034 70k ? 1k ? a v dd figure 12. equivalent csb input circuit sense 05727-036 1k ? figure 13. equivalent sense circuit vref 05727-037 6k ? figure 14. equivalent vref circuit
ad9228 rev. 0 | page 14 of 52 typical performance characteristics ?40 ?60 ?80 ?100 ?20 0 ?120 0 2 4 6 8 101214161820 05727-052 amplitude (dbfs) frequency (mhz) ain = ?0.5dbfs snr = 70.51db enob = 11.38 bits sfdr = 86.00dbc figure 15. single-tone 32k fft with f in = 2.3 mhz, f sample = 40 msps 014 12 10 8 6 4 218 16 20 amplitude (dbfs) frequency (mhz) 05727-085 ?120 ?100 ?80 ?60 ?40 ?20 0 ain = ?0.5dbfs snr = 70.38db enob = 11.40 bits sfdr = 81.13dbc figure 16. single-tone 32k fft with f in = 35 mhz, f sample = 40 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-053 ain = ?0.5dbfs snr = 70.53db enob = 11.38 bits sfdr = 86.04dbc figure 17. single-tone 32k fft with f in = 2.3 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-054 ain = ?0.5dbfs snr = 69.62db enob = 10.96 bits sfdr = 72.48dbc figure 18. single-tone 32k fft with f in = 70 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-055 ain = ?0.5dbfs snr = 68.74db enob = 10.88 bits sfdr = 72.99dbc figure 19. single-tone 32k fft with f in = 120 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-056 ain = ?0.5dbfs snr = 67.68db enob = 10.95 bits sfdr = 62.23dbc figure 20. single-tone 32k fft with f in = 170 mhz, f sample = 65 msps
ad9228 rev. 0 | page 15 of 52 0 5 10 15 20 25 30 frequency (mhz) 05727-057 ain = ?0.5dbfs snr = 67.58db enob = 10.93 bits sfdr = 68.39dbc amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 figure 21. single-tone 32k fft with f in = 190 mhz, f sample = 65 msps 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-058 ain = ?0.5dbfs snr = 65.56db enob = 10.6 bits sfdr = 62.72dbc ?120 ?100 ?80 ?60 ?40 ?20 0 figure 22. single-tone 32k fft with f in = 250 mhz, f sample = 65 msps snr/sfdr (db) encode (msps) 05727-059 60 65 70 75 80 85 90 10 15 20 25 30 35 40 2v p-p, sfdr 2v p-p, snr figure 23. snr/sfdr vs. f sample , f in = 10.3 mhz, f sample = 40 msps snr/sfdr (db) encode (msps) 05727-061 68 10 15 20 25 30 35 40 2v p-p, sfdr 2v p-p, snr 70 72 74 76 78 80 82 84 figure 24. snr/sfdr vs. f sample , f in = 35 mhz, f sample = 40 msps snr/sfdr (db) encode (msps) 05727-062 60 65 70 75 80 85 90 10 20 30 40 50 60 2v p-p, sfdr 2v p-p, snr figure 25. snr/sfdr vs. f sample , f in = 10.3 mhz, f sample = 65 msps snr/sfdr (db) encode (msps) 05727-064 68 72 70 74 76 78 82 80 84 10 20 30 40 50 60 2v p-p, sfdr 2v p-p, snr figure 26. snr/sfdr vs. f sample , f in = 35 mhz, f sample = 65 msps
ad9228 rev. 0 | page 16 of 52 snr/sfdr (db) 05727-065 0 10 20 30 40 50 60 70 80 90 100 ?60 ?50 ?40 ?30 ?20 ?10 0 f in = 10.3mhz f sample = 40msps 2v p-p, sfdr 2v p-p, snr 80db reference analog input level (dbfs) figure 27. snr/sfdr vs. analog input level, f in = 10.3 mhz, f sample = 40 msps snr/sfdr (db) analog input level (dbfs) 05727-066 0 10 20 30 40 50 60 70 80 90 100 ?60 ?50 ?40 ?30 ?20 ?10 0 f in = 35mhz f sample = 40msps 2v p-p, sfdr 2v p-p, snr 80db reference figure 28. snr/sfdr vs. analog input level, f in = 35 mhz, f sample = 40 msps snr/sfdr (db) 05727-068 0 10 20 30 40 50 60 70 80 90 100 ?60 ?50 ?40 ?30 ?20 ?10 0 f in = 10.3mhz f sample = 65msps 2v p-p, sfdr 2v p-p, snr 80db reference analog input level (dbfs) figure 29. snr/sfdr vs. analog input level, f in = 10.3 mhz, f sample = 65 msps snr/sfdr (db) 05727-070 0 10 20 30 40 50 60 70 80 90 100 ?60 ?50 ?40 ?30 ?20 ?10 0 f in = 35mhz f sample = 65msps 2v p-p, sfdr 2v p-p, snr analog input level (dbfs) 80db reference figure 30. snr/sfdr vs. analog input level, f in = 35 mhz, f sample = 65 msps ?40 ?60 ?80 ?100 ?20 0 ?120 0 2 4 6 8 101214161820 05727-049 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 80.75dbc imd2 = 85.53dbc imd3 = 80.83dbc figure 31. two-tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, f sample = 40 msps ?40 ?60 ?80 ?100 ?20 0 ?120 0 2 4 6 8 101214161820 05727-050 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 74.76dbc imd2 = 81.03dbc imd3 = 75.00dbc figure 32. two-tone 32k fft with f in1 = 70 mhz and f in2 = 71 mhz, f sample = 40 msps
ad9228 rev. 0 | page 17 of 52 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 05727-048 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 78.15dbc imd2 = 77.84dbc imd3 = 88.94dbc figure 33. two-tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-051 ain1 and ain2 = ?7dbfs sfdr = 76.75dbc imd2 = 77.56dbc imd3 = 77.01dbc figure 34. two-tone 32k fft with f in1 = 70 mhz and f in2 = 71 mhz, f sample = 65 msps snr/sfdr (db) 05727-071 50 55 60 65 70 75 80 85 90 1 10 100 1000 analog input level (dbfs) 2vp-p, sfdr 2vp-p, snr figure 35. snr/sfdr vs. f in , f sample = 65 msps snr/sfdr (db) temperature (c) 05727-072 ?40 ?20 80 60 40 20 0 60 65 70 75 80 85 90 2v p-p, sinad 2v p-p, sfdr figure 36. sinad/sfdr vs. temperature, f in = 10.3 mhz, f sample = 65 msps ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 inl (lsb) code 05727-073 0 500 1000 1500 2000 2500 3000 3500 4000 figure 37. inl, f in = 2.4 mhz, f sample = 65 msps ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (lsb) code 05727-074 0 500 1000 1500 2000 2500 3000 3500 4000 figure 38. dnl, f in = 2.4 mhz, f sample = 65 msps
ad9228 rev. 0 | page 18 of 52 cmrr (db) 05727-075 ?70 ? 30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 0 5 10 15 20 30 25 35 frequency (mhz) figure 39. cmrr vs. frequency, f sample = 65 msps number of hits (millions) 05727-086 0.2 0.4 0.6 0.8 1.0 1.2 0 n?3 n?2 n+3 n+2 n+1 n n?1 code 0.26 lsb rms figure 40. input referred noise histogram, f sample = 65 msps amplitude (dbfs) 05727-076 ?120 0 ?20 ?40 ?60 ?80 ?100 0 5 10 15 20 30 25 frequency (mhz) npr = 60.83db notch = 18.0mhz notch width = 3.0mhz figure 41. noise power ratio (npr), f sample = 65 msps fundamental level (db) 05727-077 ?10 0 ?3 ?2 ?1 ?4 ?5 ?6 ?7 ?8 ?9 0 50 100 150 200 250 300 350 400 450 500 frequency (mhz) ?3db cutoff = 315mhz figure 42. full power bandwidth vs. frequency, f sample = 65 msps
ad9228 rev. 0 | page 19 of 52 theory of operation the ad9228 architecture consists of a pipelined adc that is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the data is then serialized and aligned to the frame and output clock. analog input considerations the analog input to the ad9228 is a differential switched-capacitor circuit designed for processing differential input signals. the input can support a wide common-mode range and maintain excellent performance. an input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. ss h c par c sample c sample c par vin? h ss h vin+ h 05727-006 figure 43. switched-cap acitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 43). when the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low-q inductors or ferrite beads can be placed on each leg of the input to reduce the high differential capacitance seen at the analog inputs, thus realizing the maximum bandwidth of the adc. such use of low-q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low-pass filter at the input to limit any unwanted broadband noise. see the an-742 application note , the an-827 application note , and the analog dialogue article transformer-coupled front-end for wideband a/d converters for more information on this subject. in general, the precise values depend on the application. the analog inputs of the ad9228 are not internally dc-biased. in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = av d d /2 is recom- mended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in figure 44 and figure 45. snr/sfdr (db) analog input common mode voltage (v) 05727-078 50 55 60 65 70 75 80 85 90 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 sfdr (dbc) snr (db) figure 44. snr/sfdr vs. common-mode voltage, f in = 2.4 mhz, f sample = 65 msps snr/sfdr (db) analog input common mode voltage (v) 05727-079 50 55 60 65 70 75 80 85 90 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 sfdr (dbc) snr (db) figure 45. snr/sfdr vs. common-mode voltage, f in = 30 mhz, f sample = 65 msps
ad9228 rev. 0 | page 20 of 52 for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. these errors are reduced by the common-mode rejection of the adc. an internal reference buffer creates the positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. the output common-mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as reft = 1/2 ( avdd + vref ) refb = 1/2 ( avdd ? vref ) span = 2 ( reft ? refb ) = 2 vref it can be seen from these equations that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the vref voltage. maximum snr performance is always achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9228, the largest input span available is 2 v p-p. differential input configurations there are several ways in which to drive the ad9228 either actively or passively. in either case, the optimum performance is achieved by driving the analog input differentially. one example is by using the ad8332 differential driver. it provides excellent performance and a flexible interface to the adc (see figure 49) for baseband applications. this configuration is common for medical ultrasound systems. however, the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9228. for applications where snr is a key parameter, differential transfor- mer coupling is the recommended input configuration. two examples are shown in figure 46 and figure 47. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. 05727-008 2v p-p r r *c diff c *c diff is optional 49.9 ? 0.1 f 1k ? 1k ? agnd avdd a dt1?1wt 1:1 z ratio vin? adc ad9228 vin+ c figure 46. differential transformer coupled configuration for baseband applications adc ad9228 05727-047 2v p-p 2.2pf 1k ? 0.1 f 1k ? 1k ? avdd a dt1?1wt 1:1 z ratio 16nh 16nh 0.1 f 16nh 33 ? 33 ? 499 ? 65 ? vin+ vin? figure 47. differential transformer coupled configuration for if applications single-ended input configuration a single-ended input may provide adequate performance in cost-sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common- mode swing. if the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. a full-scale input of 2 v p-p can still be applied to the adcs vin+ pin while the vin? pin is terminated. figure 48 details a typical single-ended input configuration. 0 5727-009 2 v p- p r r 49.9 ? 0.1f 0.1f avdd 1k ? 25 ? 1k ? 1k ? a v dd vin? adc ad9228 vin+ *c diff c *c diff is optional c figure 48. single-ended input configuration ad8332 1.0k ? 1.0k ? 374 ? 187 ? 05727-007 r r c 0.1 f 187 ? 0.1 f 0.1 f 0.1 f 0.1 f10 f 0.1 f 1v p- p 0.1 f lna 120nh vga voh vip inh 22pf lmd vin lop lon vol 18nf 274 ? vin? adc ad9228 vin+ vref figure 49. differential input configuration using the ad8332
ad9228 rev. 0 | page 21 of 52 clock input considerations for optimum performance, the ad9228 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally and require no additional bias. figure 50 shows one preferred method for clocking the ad9228. the low jitter clock source is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the secondary transformer limit clock excursions into the ad9228 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9228 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsm2812 clock input 50 ? 100 ? clk? clk+ adc ad9228 min-circuits adt1?1wt, 1:1z xfmr 05727-024 figure 50. transformer coupled differential clock if a low jitter clock is available, another option is to ac-couple a differential pecl signal to the sample clock input pins as shown in figure 51. the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers offers excellent jitter performance. clock input 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? clock input 05727-025 ad9510/1/2/3/4/5 pecl driver 50 ? * 50 ? * clk clk *50 ? resistors are optional clk? clk+ adc ad9228 figure 51. differential pecl sample clock 05727-026 clock input 100 ? 0.1f 0.1f 0.1f 0.1f 50 ? * clock input ad9510/1/2/3/4/5 lvds driver 50 ? * clk clk *50 ? resistors are optional clk? clk+ adc ad9228 figure 52. differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, clk+ should be directly driven from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 53). although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages up to 3.3 v, making the selection of the drive logic voltage very flexible. 05727-027 clock input 0.1f 0.1f 0.1f 39 k ? ad9510/1/2/3/4/5 cmos driver 50 ? * optional 100 ? 0.1f clk clk *50 ? resistor is optional clk? clk+ adc ad9228 figure 53. single-ended 1.8 v cmos sample clock 05727-028 clock input 0.1f 0.1f 0.1f ad9510/1/2/3/4/5 cmos driver 50 ? * optional 100 ? clk clk *50 ? resistor is optional 0.1f clk? clk+ adc ad9228 figure 54. single-ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9228 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9228. when the dcs is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. the dcs function cannot be turned off. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately 10 clock cycles to allow the dll to acquire and lock to the new rate.
ad9228 rev. 0 | page 22 of 52 clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr degradation = 20 log 10 [1/2 f a t j ] in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 55). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9228. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs (visit www.analog.com ). 1 10 100 1000 05727-038 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125 ps 0.25 ps 0.5 ps 1.0 ps 2.0 ps analog input frequency (mhz) 10 bits rms clock jitter requirement snr (db) figure 55. ideal snr vs. input frequency and jitter power dissipation and power-down mode as shown in figure 56 and figure 57, the power dissipated by the ad9228 is proportional to its sample rate. the digital power dissipation does not vary much because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. 10 20 15 30 35 25 40 current (ma) encode (msps) 0 5727-089 180 220 200 240 300 340 320 360 260 280 0 20 40 100 140 120 180 160 60 80 drvdd current total power avdd current power (mw) figure 56. supply current vs. f sample for f in = 10.3 mhz, f sample = 40 msps 10 20 30 40 50 60 current (ma) power (mw) encode (msps) 05727-081 0 50 100 150 200 250 300 340 320 360 380 400 420 440 460 480 drvdd current total power avdd current figure 57. supply current vs. f sample for f in = 10.3 mhz, f sample = 65 msps
ad9228 rev. 0 | page 23 of 52 by asserting the pdwn pin high, the ad9228 is placed in power-down mode. in this state, the adc typically dissipates 3 mw. during power-down, the lvds output drivers are placed in a high impedance state. the ad9228 returns to normal operating mode when the pdwn pin is pulled low. this pin is both 1.8 v and 3.3 v tolerant. in power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, pll, and biasing networks. the decoupling capacitors on reft and refb are discharged when entering power-down mode and must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. with the recommended 0.1 f and 2.2 f decoupling capacitors on reft and refb, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 375 s to restore full operation. there are a number of other power-down options available when using the spi port interface. the user can individually power down each channel or put the entire device into standby mode. this allows the user to keep the internal pll powered when fast wake-up times (~600 ns) are required. see the memory map section for more details on using these features. digital outputs and timing the ad9228 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option similar to the ieee 1596.3 standard using the sdio/odm pin or via the spi. this lvds standard can further reduce the overall power dissipation of the device by roughly 15 mw. see the sdio/odm pin section or table 15 in the memory map section for more information. the lvds driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the ad9228 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. no far-end receiver termination and poor differential trace routing may result in timing errors. it is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. an example of the fco and data stream with proper trace length and position can be found in figure 58. 05727-045 ch1 200mv/div = dco ch2 200mv/div = data ch3 500mv/div = fco 2.5ns/div figure 58. lvds output timing example in ansi mode (default) an example of the lvds output using the ansi standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths less than 24 inches on regular fr-4 material is shown in figure 59. figure 60 shows an example of when the trace lengths exceed 24 inches on regular fr-4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal ter- mination (increasing the current) of all four outputs in order to drive longer trace lengths (see figure 61). even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when this option is used. also notice in figure 61 that the histogram has improved. see the memory map section for more details.
ad9228 rev. 0 | page 24 of 52 05727-043 100 50 0 ?100ps ?0ps 100ps tie jitter histogram (hits) 500 ?500 0 ?1ns ?0.5ns 0ns 0.5ns 1ns eye diagram voltage (v) eye: all bits uls: 10000/15600 figure 59. data eye for lvds outputs in ansi mode with trace lengths less than 24 inches on standard fr-4 05727-044 200 ?200 0 ?1ns ?0.5ns 0ns 0.5ns 1ns eye diagram voltage (v) eye: all bits uls: 9600/15600 100 50 0 ?150ps ?100ps ?50ps ?0ps 50ps 100ps 150ps tie jitter histogram (hits) figure 60. data eye for lvds outputs in ansi mode with trace lengths greater than 24 inches on standard fr-4 100 50 0 ?150ps ?100ps ?50ps ?0ps 50ps 100ps 150ps tie jitter histogram (hits) 05727-042 200 400 ?200 ?400 0 ?1ns ?0.5ns 0ns 0.5ns 1ns eye diagram voltage (v) eye: all bits uls: 9599/15599 figure 61. data eye for lvds outputs in ansi mode with 100 termination on and trace lengths greater than 24 inches on standard fr-4 the format of the output data is offset binary by default. an example of the output coding format can be found in table 8. if it is desired to change the output data format to twos complement, see the memory map section. table 8. digital output coding code (vin+) ? (vin?), input span = 2 v p-p (v) digital output offset binary (d11 ... d0) 4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 2047 ?0.000488 0111 1111 1111 0 ?1.00 0000 0000 0000 data from each adc is serialized and provided on a separate channel. the data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 mbps (12 bits 65 msps = 780 mbps). the lowest typical conversion rate is 10 msps. however, if lower sample rates are required for a specific application, the pll can be set up for encode rates lower than 10 msps via the spi. this allows encode rates as low as 5 msps. see the memory map section to enable this feature.
ad9228 rev. 0 | page 25 of 52 two output clocks are provided to assist in capturing data from the ad9228. the dco is used to clock the output data and is equal to six times the sampling clock (clk) rate. data is clocked out of the ad9228 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. the frame clock out (fco) is used to signal the start of a new output byte and is equal to the sampling clock rate. see the timing diagram shown in figure 2 for more information. table 9. flex output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) same yes 0010 +full-scale short 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) same yes 0011 ?full-scale short 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) same yes 0100 checker board 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit) no 0101 pn sequence long 1 n/a n/a yes 0110 pn sequence short 1 n/a n/a yes 0111 one/zero word toggle 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) no 1000 user input register 0x19 to register 0x 1a register 0x1b to register 0x1c no 1001 one/zero bit toggle 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) n/a no 1010 1 sync 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) n/a no 1011 one bit high 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) n/a no 1100 mixed frequency 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) n/a no 1 pn, or pseudorandom number, sequence is dete rmined by the number of bits in the shift register. the long sequence is 23 bits an d the short sequence is 9 bits. how the sequence is generated and utilized is describe d in the itu o.150 standard. in general, the polynomial, x23 + x1 8 + 1 (long) and x9 + x5 + 1 (short), defines the pseudorandom sequence.
ad9228 rev. 0 | page 26 of 52 when using the serial port interface (spi), the dco phase can be adjusted in 60 increments relative to the data edge. this enables the user to refine system timing margins if required. the default dco timing, as shown in figure 2, is 90 relative to the output data edge. an 8-, 10-, and 14-bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lower and higher resolution systems. when changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. see figure 3 for the 10-bit example. however, when using the 14-bit option, the data stream stuffs two 0s at the end of the normal 14-bit serial data. when using the spi, all of the da ta outputs can also be inverted from their nominal state. this is not to be confused with inverting the serial stream to an lsb-first mode. in default mode, as shown in figure 2, the msb is represented first in the data output serial stream. however, this can be inverted so that the lsb is represented first in the data output serial stream (see figure 4). there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 9 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. it should be noted that some patterns may not adhere to the data format select option. in addition, customer user patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. all test mode options can support 8- to 14-bit word lengths in order to verify data capture to the receiver. please consult the memory map section for information on how to change these additional digital output timing features through the serial port interface or spi. sdio/odm pin this pin is for applications that do not require spi mode operation. the sdio/odm pin can enable a low power, reduced signal option similar to the ieee 1596.3 reduced range link output standard if this pin and the csb pin are tied to avdd during device power- up. this option should only be used when the digital output trace lengths are less than 2 inches in length to the lvds receiver. the fco, dco, and outputs still work as usual, but the lvds signal swing of all channels is reduced from 350 mv p-p to 200 mv p-p. this output mode allows the user to further lower the power on the drvdd supply. for applications where this pin is not used, it should be tied low. in this ca se, the device pin can be left open, and the 30 k internal pull-down resistor pulls this pin low. this pin is only 1.8 v tolerant. if applications require this pin to be driven from a 3.3 v logic level, insert a 1 k resistor in series with this pin to limit the current. table 10. output driver mode pin settings selected odm odm voltage resulting output standard resulting fco and dco normal operation 10 k to agnd ansi-644 (default) ansi-644 (default) odm avdd low power, reduced signal option low power, reduced signal option sclk/dtp pin this pin is for applications that do not require spi mode operation. the serial clock/digital test pattern (sclk/dtp) pin can enable a single digital test pattern if this pin and the csb pin are held high during device power-up. when the dtp is tied to avdd, all the adc channel outputs shift out the following pattern: 1000 0000 0000. the fco and dco outputs still work as usual while all channels shift out the repeatable test pattern. this pattern allows the user to perform timing alignment adjustments among the fco, dco, and output data. for normal operation, this pin should be tied to agnd through a 10 k resistor. this pin is both 1.8 v and 3.3 v tolerant. table 11. digital test pattern pin settings selected dtp dtp voltage resulting d+ and d? resulting fco and dco normal operation 10 k to agnd normal operation normal operation dtp avdd 1000 0000 0000 normal operation additional and custom test patterns can also be observed when commanded from the spi port. consult the memory map section to choose from the different options available. csb pin the chip select bar (csb) pin should be tied to avdd for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. this pin is both 1.8 v and 3.3 v tolerant. rbias pin to set the internal core bias current of the adc, place a resistor (nominally equal to 10.0 k) to ground at the rbias pin. the resistor current is derived on-chip and sets the adcs avdd current to a nominal 232 ma at 65 msps. therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. if sfdr performance is not as critical as power, simply adjust the adc core current to achieve a lower power. figure 62 and figure 63 show the relationship between the dynamic range and power as the rbias resistance is changed. nominally, we use a 10.0 k value, as indicated by the dashed line.
ad9228 rev. 0 | page 27 of 52 05727-063 90 70 75 85 80 65 75 50 55 65 70 60 2 18202224 4 6 8 12 14 16 10 sfdr (dbc) resistance (k ? ) snr (dbc) snr sfdr figure 62. sfdr vs. rbias 3 8 13 18 23 iavdd (ma) resistance (k ? ) 05727-082 0 100 200 400 600 500 300 figure 63. iavdd vs. rbias voltage reference a stable and accurate 0.5 v voltage reference is built into the ad9228. this is gained up by a factor of 2 internally, setting v ref to 1.0 v, which results in a full-scale differential input span of 2 v p-p. the v ref is set internally by default; however, the vref pin can be driven externally with a 1.0 v reference to achieve more accuracy. when applying the decoupling capacitors to the vref, reft, and refb pins, use ceramic low esr capacitors. these capacitors should be close to the adc pins and on the same layer of the pcb as the ad9228. the recommended capacitor values and configurations for the ad9228 reference pin can be found in figure 64. table 12. reference settings selected mode sese voltage resulting vref (v) resulting differential span (v pp) external reference avdd n/a 2 external reference internal, 2 v p-p fsr agnd to 0.2 v 1.0 2.0 internal reference operation a comparator within the ad9228 detects the potential at the sense pin and configures the reference. if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 64), setting vref to 1 v. the reft and refb pins establish their input span of the adc core from the reference configuration. the analog input full- scale range of the adc equals twice the voltage at the reference pin for either an internal or an external reference configuration. if the reference of the ad9228 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. figure 66 depicts how the internal reference voltage is affected by loading. 1f 0.1f v ref sense 0.5v reft 0.1f 0.1f 2.2f 0.1f refb select logic adc core + 05727-010 vin? vin+ figure 64. internal reference configuration 1f 0.1f v ref sense avdd 0.5v reft 0.1f 0.1f 2.2f 0.1f refb select logic adc core + 05727-046 vin? vin+ figure 65. external reference operation
ad9228 rev. 0 | page 28 of 52 external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac- teristics. figure 67 shows the typical drift characteristics of the internal reference in 1 v mode. when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. the external reference is loaded with an equivalent 6 k load. an internal reference buffer generates the positive and negative full-scale references, reft and refb, for the adc core. therefore, the external reference must be limited to a nominal of 1.0 v. 01.0 0.5 2.0 1.5 3.0 2.5 3.5 v ref error (%) current load (ma) 05727-083 ?30 ?5 ?10 ?15 ?20 ?25 5 0 figure 66. v ref accuracy vs. load v ref error (%) 05727-084 ?0.05 0 0.05 0.10 ?0.10 0.15 ?0.15 0.20 ?0.20 ?40 ?20 80 60 40 20 0 temperature (c) figure 67. typical v ref drift
ad9228 rev. 0 | page 29 of 52 serial port interface (spi) the ad9228 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. this gives the user added flexibility and customization depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided down into fields, as doc- umented in the memory map section. detailed operational information can be found in the analog devices user manual interfacing to high speed adcs via spi . there are three pins that define the serial port interface or spi to this particular adc. they are the sclk, sdio, and csb pins. the sclk (serial clock) is used to synchronize the read and write data presented to the adc. the sdio (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb (chip select bar) is an active low control that enables or disables the read and write cycles (see table 13 ) . table 13. serial port pins pin function sclk serial clock. the serial shif t clock in. sclk is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin. the typical role for this pin is an input or output, depending on the instruction sent and th e relative position in the timing frame. csb chip select bar (active low). this control gates the read and write cycles. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing sequence. during an instruction phase, a 16-bit inst ruction is transmitted followed by one or more data bytes, whic h is determined by bit fields w0 and w1. an example of the serial timing and its definitions can be found in figure 68 and table 14. in normal operation, csb is used to signal to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdio to pr ocess instructions. normally, csb remains low until the comm unication cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing ol d microcontrollers enough time to transfer data into shift registers. csb can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the csb is taken high to end the communication cycle. this allows complete memory transfers without having to provide additional instruc- tions. regardless of the mode, if csb is taken high in the middle of any byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port can be configured to operate in different manners. for applications that do not require a control port, the csb line can be tied and held high. this places the remainder of the spi pins in their secondary mode as defined in the serial port interface (spi) section. csb can also be tied lo w to enable 2-wire mode. when csb is tied low, sclk and sdio are the only pins required for communication. although the device is synchronized during power-up, caution must be exerci sed when using this mode to ensure that the serial port re mains synchronized with the csb line. when operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines if the serial frame is a read or writ e operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb- or lsb-first mode. msb-first mode is the default at power-up and can be changed by adjusting the configuration register. for more information about this and other features, see the user manual interfacing to high speed adcs via spi . hardware interface the pins described in table 13 compose the physical interface between the users programming device and the serial port of the ad9228. the sclk and csb pins function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. this interface is flexible enough to be controlled by either serial proms or pic mirocontrollers. this provides the user an alternative method, other than a full spi controller, to program the adc (see the an-812 application note ). if the user chooses not to use the spi interface, these pins serve a dual function and are associated with secondary functions when the csb is strapped to avdd during device power-up. see the theory of operation section for details on which pin- strappable functions are supported on the spi pins.
ad9228 rev. 0 | page 30 of 52 don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 05727-012 figure 68. serial timing details table 14. serial timing definitions parameter timing (minimum, ns) description t ds 5 set-up time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 set-up time between csb and sclk t h 2 hold time between csb and sclk t hi 16 minimum period that sclk should be in a logic high state t lo 16 minimum period that sclk should be in a logic low state
ad9228 rev. 0 | page 31 of 52 memory map reading the memory map table each row in the memory map table has eight address locations. the memory map is roughly divided into three sections: chip configuration register map (address 0x00 to address 0x02), device index and transfer register map (address 0x05 and address 0xff), and program register map (address 0x08 to address 0x25). the left-hand column of the memory map indicates the register address number in hexadecimal. the default value of this address is shown in hexadecimal in the right-hand column. the bit 7 (msb) column is the start of the default hexadecimal value given. for example, hexadecimal address 0x 09, clock, has a hexadecimal default value of 0x01. this means bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 6 at this address, the duty cycle stabilizer turns off. for more information on this and other functions, consult the user manual interfacing to high speed adcs via spi . reserved locations undefined memory locations should not be written to except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values coming out of reset, critical registers are preloaded with default values. these values are indicated in table 15, where an x refers to an undefined feature. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit.
ad9228 rev. 0 | page 32 of 52 table 15. memory map register addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 00 chip_port_config 0 lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 soft reset 1 = on 0 = off (default) lsb first 1 = on 0 = off (default) 0 0x18 the nibbles should be mirrored so that lsb- or msb-first mode registers correctly regardless of shift mode. 01 chip_id 8-bit chip id bits 7:0 (ad9228 = 0x02), (default) 0x02 default is unique chip id, different for each device. this is a read- only register. 02 chip_grade x child id 6:4 (identify device variants of chip id) 000 = 65 msps, 001 = 40 msps x x x x read only child id used to differentiate graded devices. device index and transfer registers 05 device_index_a x x clock channel dco 1 = on 0 = off (default) clock channel fco 1 = on 0 = off (default) data channel d 1 = on (default) 0 = off data channel c 1 = on (default) 0 = off data channel b 1 = on (default) 0 = off data channel a 1 = on (default) 0 = off 0x0f bits are set to determine which on-chip device receives the next write command. ff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. adc functions 08 modes x x x x x internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 0x00 determines various generic modes of chip operation. 09 clock x x x x x x x duty cycle stabilizer 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer on and off. 0d test_io user test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test modesee table 9 in the digital outputs and timing section 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checker board output 0101 = pn 23 sequence 0110 = pn 9 0111 = one/zero word toggle 1000 = user input 1001 = one/zero bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) 0x00 when set, the test data is placed on the output pins in place of normal data.
ad9228 rev. 0 | page 33 of 52 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 14 output_mode x 0 = lvds ansi (default) 1 = lvds low power, (ieee 1596.3 similar) x x x output invert 1 = on 0 = off (default) 00 = offset binary (default) 01 = twos complement 0x00 configures the outputs and the format of the data. 15 output_adjust x x output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100 x x x x 0x00 determines lvds or other output properties. primarily func- tions to set the lvds span and common-mode levels in place of an external resistor. 16 output_phase x x x x 0011 = output clock phase adjust (0000 through 1010) (default: 180 relative to data edge) 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge 0100 = 240 relative to data edge 0101 = 300 relative to data edge 0110 = 360 relative to data edge 0111 = 420 relative to data edge 1000 = 480 relative to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge 0x03 on devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. internal latching is unaffected. 19 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 1 lsb. 1a user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user-defined pattern, 1 msb. 1b user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 2 lsb. 1c user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user-defined pattern, 2 msb. 21 serial_contr ol lsb first 1 = on 0 = off (default) x x x <10 msps, low encode rate mode 1 = on 0 = off (default) 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 serial stream control. default causes msb first and the native bit stream (global). 22 serial_ch_stat x x x x x x channel output reset 1 = on 0 = off (default) channel power- down 1 = on 0 = off (default) 0x00 used to power down individual sections of a converter (local).
ad9228 rev. 0 | page 34 of 52 power and ground recommendations when connecting power to the ad9228, it is recommended that two separate 1.8 v supplies be used: one for analog (avdd) and one for digital (drvdd). if only one supply is available, it should be routed to the avdd first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the drvdd. the user can employ several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts with minimal trace length. a single pc board ground plane should be sufficient when using the ad9228. with proper decoupling and smart parti- tioning of the pc boards analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the underside of the adc is connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9228. an exposed continuous copper plane on the pcb should mate to the ad9228 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the two during the reflow process. using one continuous plane with no partitions only guarantees one tie point between the adc and pcb. see figure 69 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp), at www.analog.com . silkscreen p a rtition pin 1 indicator 05727 -013 figure 69. typical pcb layout
ad9228 rev. 0 | page 35 of 52 evaluation board the ad9228 evaluation board provides all of the support cir- cuitry required to operate the adc in its various modes and configurations. the converter can be driven differentially through a transformer (default) or through the ad8332 driver. the adc can also be driven in a single-ended fashion. separate power pins are provided to isolate the dut from the ad8332 drive circuitry. each input configuration can be selected by proper connection of various jumpers (see figure 72 to figure 76). figure 70 shows the typical bench characterization setup used to evaluate the ac performance of the ad9228. it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure 72 to figure 80 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. power supplies this evaluation board comes with a wall-mountable switching power supply that provides a 6 v, 2 a maximum output. simply connect the supply to the rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at p503. once on the pc board, the 6 v supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. when operating the evaluation board in a nondefault condition, l504 to l507 can be removed to disconnect the switching power supply. this enables the user to bias each section of the board individually. use p501 to connect a different supply for each section. at least one 1.8 v supply is needed with a 1 a current capability for avdd_dut and drvdd_dut; however, it is recommended that separate supplies be used for both analog and digital. to operate the evaluation board using the vga option, a separate 5.0 v analog supply is needed. the 5.0 v supply, or avdd_5 v, should have a 1 a current capability. to operate the evaluation board using the spi and alternate clock options, a separate 3.3 v analog supply is needed in addition to the other supplies. the 3.3 v supply, or avdd_3.3 v, should have a 1 a current capability as well. input signals when connecting the clock and analog source, use clean signal generators with low phase noise, such as rohde & schwarz smhu or hp8644 signal generators or the equivalent. use a 1 m, shielded, rg-58, 50 coaxial cable for making connections to the evalu- ation board. enter the desired frequency and amplitude from the adc specifications tables. typically, most adi evaluation boards can accept ~2.8 v p-p or 13 dbm sine wave input for the clock. when connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. adi uses tte, allen avionics, and k&l types of band-pass filters. the filter should be connected directly to the evaluation board if possible. output signals the default setup uses the hsc-adc-fpga high speed deserialization board to deserialize the digital output data and convert it to parallel cmos. these two channels interface directly with the adi standard dual-channel fifo data capture board ( hsc-adc-evala-dc ). two of the four channels can then be evaluated at the same time. for more information on channel settings on these boards and their optional settings, visit www.analog.com/fifo . rohde & schwarz, smhu, 2v p-p signal synthesizer rohde & schwarz, smhu, 2v p-p signal synthesizer band-pass filter xfmr input clk cha?chd 12-bit serial lvds 2 ch 12-bit parallel cmos usb connection ad9228 evaluation board hsc-adc-fpga high speed deserialization board 05727 -014 hsc-adc-evala-dc fifo data capture board pc running adc analyzer and spi user software 1.8v ?+ ?+ avdd_dut avdd_3.3v drvdd_dut gnd gnd ?+ 5.0v gnd avdd_5v 1.8v 6v dc 2a max wall outlet 100v to 240v ac 47hz to 63hz switching power supply ?+ gnd 3.3v ?+ 1.5v_fpga 3.3v_d gnd 3.3v ?+ gnd 1.5v ?+ vcc gnd 3.3v spi spi spi spi figure 70. evaluation board connection
ad9228 rev. 0 | page 36 of 52 default operation and jumper selection settings the following is a list of the default and optional settings or modes allowed on the ad9228 rev. a evaluation board. ? power: connect the switching power supply that is supplied in the evaluation kit between a rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz and p503. ? ain: the evaluation board is set up for a transformer- coupled analog input with optimum 50 impedance matching out to 200 mhz (see figure 71). for more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. the common mode of the analog inputs is developed from the center tap of the transformer or avdd_dut/2. 0 amplitude (dbfs) frequency (mhz) 05727-088 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 50 100 150 200 250 300 350 400 450 500 ?3db cutoff = 200mhz figure 71. evaluation bo ard full power bandwidth ? vref: vref is set to 1.0 v by tying the sense pin to ground, r237. this causes the adc to operate in 2.0 v p-p full-scale range. a separate external reference option using the adr510 or adr520 is also included on the evaluation board. simply populate r231 and r235 and remove c214. proper use of the vref options is noted in the volt age reference section. ? rbias: rbias has a default setting of 10 k (r201) to ground and is used to set the adc core bias current. to further lower the core power (excluding the lvds driver supply), simply change the resistor setting. however, performance of the adc will degrade depending on the resistor chosen. see rbias section for more information. ? clock: the default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (t201) that adds a very low amount of jitter to the clock path. the clock input is 50 terminated and ac-coupled to handle single-ended sine wave types of inputs. the transformer converts the single-ended input to a differential signal that is clipped before entering the adc clock inputs. a differential lvpecl clock can also be used to clock the adc input using the ad9515 (u202). simply populate r225 and r227 with 0 resistors and remove r217 and r218 to disconnect the default clock path inputs. in addition, populate c207 and c208 with a 0.1 f capacitor and remove c210 and c211 to disconnect the default cloth path outputs. the ad9515 has many pin-strappable options that are set to a default working condition. consult the ad9515 data sheet for more information about these and other options. if using an oscillator, two oscillator footprint options are also available (osc201) to check the adc performance. j205 gives the user flexibility in using the enable pin, which is common on most oscillators. ? pdwn: to enable the power-down feature, simply short j201 to the on position (avdd) on the pdwn pin. ? sclk/dtp: to enable one of the two digital test patterns on the digital outputs of the adc, use j204. if j204 is tied to avdd during device power-up, test pattern 1000 0000 0000 will be enabled. see the sclk/dtp pin section for details. ? sdio/odm: to enable the low power, reduced signal option similar to the ieee 1595.3 reduced range link lvds output standard, use j203. if j203 is tied to avdd during device power-up, it enables the lvds outputs in a low power, reduced signal option from the default ansi standard. this option changes the signal swing from 350 mv p-p to 200 mv p-p, which reduces the power of the drvdd supply. see the sdio/odm pin section for more details. ? csb: to enable the spi information on the sdio and sclk pins that is to be processed, simply tie j202 low in the always enable mode. to ignore the sdio and sclk information, tie j202 to avdd. ? d+, d?: if an alternative data capture method to the setup described in figure 72 is used, optional receiver terminations, r206 to r211, can be installed next to the high speed back- plane connector.
ad9228 rev. 0 | page 37 of 52 alternative analog input drive configuration the following is a brief description of the alternative analog input drive configuration using the ad8332 dual vga. if this particular drive option is in use, some components may need to be populated, in which case all the necessary components are listed in table 16. for more details on the ad8332 dual vga, including how it works and its optional pin settings, consult the ad8332 data sheet. to configure the analog input to drive the vga instead of the default transformer option, the following components need to be removed and/or changed. ? remove r102, r115, r128, r141, t101, t102, t103, and t104 in the default analog input path. ? populate r101, r114, r127, and r140 with 0 resistors in the analog input path. ? populate r106, r107, r119, r120, r132, r133, r144, and r145 with 10 k resistors to provide an input common- mode level to the analog input. ? populate r105, r113, r118, r124, r131, r137, r151, and r160 with 0 resistors in the analog input path. currently, l301 to l308 and l401 to l408 are populated with 0 resistors to allow signal connection. this area allows the user to design a filter if additional requirements are necessary.
ad9228 rev. 0 | page 38 of 52 channel a p101 ain ain vga input connection vga input connection vga input connection vga input connection 1 2 3 6 5 4 t101 cm1 cm1 fb103 10 ? fb102 10 ? fb101 10 ? c104 2.2pf vin_a vin_a p102 dnp cm1 inh1 ch_a avdd_dut ch_a r104 0 ? avdd_dut a vdd_dut c106 dnp c107 0.1f c103 dnp c105 dnp c101 0.1f c102 0.1f e101 r161 499 ? r152 dnp r113 dnp r105 dnp r110 33 ? r107 dnp r106 dnp r112 1k ? r111 1k ? r108 33 ? r101 dnp r102 64.9 ? r103 0 ? r109 1k ? channel b p103 ain 1 2 3 6 5 4 t102 cm2 cm2 fb106 10 ? fb105 10 ? fb104 10 ? c111 2.2pf vin_b vin_b p104 dnp cm2 inh2 ch_b avdd_dut ch_b r116 0 ? avdd_dut avdd_dut c113 dnp c114 0.1f c110 dnp c112 dnp c108 0.1f c109 0.1f e102 r162 499 ? r153 dnp r124 dnp r118 dnp r122 33 ? r120 dnp r119 dnp r126 1k ? r125 1k ? r121 33 ? r114 dnp r115 64.9 ? r117 0 ? r123 1k ? channel c p105 ain 1 2 3 6 5 4 t103 cm3 cm3 fb109 10 ? fb108 10 ? fb107 10 ? c118 2.2pf vin_c vin_c p106 dnp cm3 inh3 ch_c avdd_dut ch_c r130 0 ? avdd_dut avdd_dut c120 dnp c121 0.1f c117 dnp c119 dnp c115 0.1f c116 0.1f e103 r163 499 ? r154 dnp r137 dnp r131 dnp r136 33 ? r133 dnp r132 dnp r139 1k ? r138 1k ? r134 33 ? r127 dnp r128 64.9 ? r129 0 ? r135 1k ? channel d p107 ain 1 2 3 6 5 4 t104 cm4 cm4 fb112 10 ? fb111 10 ? r143 0 ? c125 2.2pf vin_d vin_d p108 dnp cm4 inh4 ch_d avdd_dut ch_d fb110 10 ? avdd_dut avdd_dut c127 dnp c128 0.1f c124 dnp c126 dnp r159 dnp c122 0.1f c123 0.1f e104 r164 499 ? r155 dnp r160 dnp r151 dnp r147 33 ? r145 dnp r144 dnp r150 1k ? r149 1k ? r146 33 ? r140 dnp r141 64.9 ? r142 0 ? r148 1k ? r156 dnp r157 dnp 05727-015 ain ain ain r158 dnp dnp: do not populate figure 72. evaluation board schematic, dut analog inputs
ad9228 rev. 0 | page 39 of 52 csb c217 0.1f c220 0.1f c221 0.1f c218 0.1f c219 0.1f c223 0.1f c222 0.1f avdd_3.3v clk clkb gnd gnd_pad out0 out0b out1 out1b rset s0 s1 s10 s2 s3 s4 s5 s6 s7 s8 s9 syncb vref vs signal=dnc;27,28 input encode enc enc dnp clock circuit optional clock drive circuit disable enable optional clock oscillator c224 0.1f r214 10k ? r215 10k ? 14 7 8 1 3 5 12 10 osc201 cb3lv-3c c207 0.1f dnp c208 0.1f dnp c209 0.1f dnp c215 0.1f dnp c211 0.1f c210 0.1f e202 1 e201 p201 p203 avdd_3.3v 12 6 7 25 8 16 9 15 10 14 11 13 18 19 23 22 32 1 31 33 u202 signal=avdd_3.3v;4,17,20,21,24,26,29,30 ad9515 3 2 1 cr201 hsms2812 r220 dnp r240 243 ? r243 100 ? r241 243 ? r242 100 ? 6 5 4 3 2 1 t201 1 2 3 j205 c205 0.1f c216 0.1f r213 49.9k ? r216 0 ? r221 10k ? r212 0 ? dnp r219 dnp s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 opt_clk opt_clk clk avdd_3.3v opt_clk opt_clk clk clk lvpecl output lvds output clk avdd_3.3v 1 1 e203 avdd_3.3v vcc gnd out oe oe' gnd' vcc' out' r244 dnp r245 0 ? s4 s0 s5 s3 s2 s1 avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v r246 dnp r247 0 ? r248 dnp r249 0 ? r250 dnp r251 0 ? r252 dnp r253 0 ? r254 dnp r255 0 ? r256 dnp r257 0 ? s10 s6 s9 s8 s7 avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v r258 dnp r259 0 ? r260 dnp r261 0 ? r262 dnp r263 0 ? r264 dnp r265 0 ? a1 a2 a3 a4 a5 a6 a7 a8 a9 gndab1 gndab10 gndab2 gndab3 gndab4 gndab5 gndab6 gndab7 gndab8 gndab9 gndcd1 gndcd10 gndcd2 gndcd3 gndcd4 gndcd5 gndcd6 gndcd7 gndcd8 gndcd9 headerm1469169_1 r205?r211 optional output terminations digital outputs csb3__chb sdi_chb sdo_cha csb2_cha csb1_cha sdi_cha sclk_cha r206 dnp r211 dnp r210 dnp r209 dnp r208 dnp p202 r207 dnp sclk_chb dco c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c10 50 49 48 47 46 45 44 43 42 41 20 19 18 17 16 15 14 13 12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 11 chd chc chb cha fco dco chd chc chb cha fco sdo_chb csb4_chb 40 60 1 9 21 22 4 5 25 6 26 8 31 32 33 34 35 36 37 38 29 10 30 2 23 3 24 28 51 52 53 54 55 56 57 58 39 59 7 27 odm enable clk avdd clk+ clk? d+a d+b d+c d+d d?a d?b d?c d?d dco+ dco? drgnd drvdd fco+ fco? pdwn rbias refb reft sclk/dtp sdio/odm sense vin+a vin+b vin+c vin+d vin?a vin?b vin?c vin?d vref avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd drvdd drgnd reference decoupling c204 0.1f c203 0.1f c202 2.2f c201 0.1f r205 10k ? r203 100k ? r204 100k ? 3 2 1 j201 1 8 730 20 18 16 14 19 17 15 13 24 23 11 12 22 21 10 2 25 26 27 32 35 36 39 45 46 5 6 9 31 40 43 44 28 29 41 33 38 47 4 34 37 48 3 42 u201 ad9228lfcsp r202 100k ? csb_dut 1 2 3 j202 sdio_odm 1 2 3 j 2 0 3 s c l k _ d t p 3 2 1 j 2 0 4 g n d g n d r 2 0 1 1 0 k ? avdd_dut cha chb chc chd cha chb chc dco dco fco fco a v d d _ d u t a v d d _ d u t a v d d _ d u t avdd_dut avdd_dut vsense_dut v i n _ a vin_b vin_c v i n _ a vin_b vref_dut a v d d _ d u t a v d d _ d u t c l k chd a v d d _ d u t a v d d _ d u t a v d d _ d u t a v d d _ d u t a v d d _ d u t v i n _ d vin_c v i n _ d d r v d d _ d u t d r v d d _ d u t a v d d _ d u t p w d n e n a b l e a l w a y s e n a b l e s p i d t p e n a b l e u 2 0 3 cw v r e f = 1 v v r e f = e x t e r n a l v r e f = 0 . 5 v r e m o v e c 2 1 4 w h e n u s i n g e x t e r n a l v r e f v r e f = 0 . 5 v ( 1 + r 2 3 2 / r 2 3 3 ) v r e f s e l e c t r e f e r e n c e c i r c u i t c 2 1 2 0 . 1 f r 2 2 9 4 . 9 9 k ? c 2 1 4 1 f c 2 1 3 0 . 1 f r 2 3 0 1 0 k ? r 2 3 1 d n p d n p v s e n s e _ d u t r 2 2 8 4 7 0 k ? d n p d n p r 2 3 4 d n p r 2 3 5 d n p r 2 3 6 d n p r 2 3 7 0 ? d n p a v d d _ d u t v r e f _ d u t avdd_dut t r i m / n c gnd v o u t a d r 5 1 0 / 2 0 1 v r 2 3 2 d n p r 2 3 3 d n p r 2 1 7 0 ? r 2 1 8 0 ? r 2 2 5 0 ? d n p r 2 2 6 4 9 . 9 ? d n p r 2 2 7 0 ? d n p r 2 3 8 d n p r 2 3 9 1 0 k ? c 2 0 6 0 . 1 f r 2 2 3 0 ? r 2 2 4 0 ? r 2 2 2 4 . 0 2 k ? 2 3 5 n c = n o c o n n e c t r266 100k ? - dnp r267 100k ? - dnp c l i p s i n e o u t ( d e f a u l t ) d n p : d o n o t p o p u l a t e o p t i o n a l e x t r e f figure 73. evaluation board schematic, dut, vr ef, clock inputs, and digital output interface
ad9228 rev. 0 | page 40 of 52 cw power down enable (0-1v = disable power) external variable gain drive variable gain circuit (0-1.0v dc) r319 10k ? 12 jp301 gnd vg r320 39k ? vg avdd_5v hilo pin hi gain range = 2.25v-5.0v lo gain range = 0-1.0v r315 10k ? l310 120nh c322 0.018f c317 0.018f r316 274 ? r317 274 ? c312 0.1f c325 0.1f c313 0.1f c314 0.1f l309 120nh c318 22pf c321 0.1f c320 0.1f c316 0.1f r318 10k ? c323 22pf c319 0.1f c324 0.1f inh4 inh3 avdd_5v avdd_5v c326 10f c315 10f optional vga drive circuit for channels c and d c311 0.1f r312 10k ? r313 10k ? dnp c303 dnp l304 0 ? r303 dnp l308 0 ? 24 17 20 23 18 22 19 21 r304 dnp l306 0 ? l305 0 ? l302 0 ? l303 0 ? l307 0 ? c308 0.1f c307 0.1f c306 0.1f c305 0.1f r310 187 ? r309 187 ? r308 187 ? r307 187 ? c302 dnp l301 0 ? c301 dnp r305 374 ? r306 374 ? ch_c ch_d ch_d ch_c avdd_5v avdd_5v avdd_5v c304 dnp r301 dnp r302 dnp 31 10 26 25 14 27 3 6 4 5 1 8 32 9 15 16 vg 28 13 29 12 30 11 2 7 com1 com2 enbl enbv gain hilo inh1 inh2 lmd1 lmd2 lon1 lon2 lop1 lop2 mode nc rclmp vcm1 vcm2 vin1 vin2 vip1 vip2 voh1 voh2 vol1 vol2 vps1 vps2 vpsv ad8332 comm comm r311 10k ? dnp r314 10k ? dnp c310 0.1f c309 1000pf rclamp pin hilo pin = lo = 50mv hilo pin = h = 75mv 05727-017 mode pin positive gain slope = 0-1.0v negative gain slope = 2.25v-5.0v u301 populate l301-l308 with 0 ? resistors or design your own filter. dnp: do not populate figure 74. evaluation board schematic, optional dut analog input drive
ad9228 rev. 0 | page 41 of 52 mode pin positive gain slope = 0-1.0v negative gain slope = 2.25v-5.0v hilo pin hi gain range = 2.25v-5.0v lo gain range = 0-1.0v r414 10k ? l410 120nh c420 0.018f c415 0.018f r415 274 ? c410 0.1f c425 0.1f c423 0.1f c424 0.1f l409 120nh c418 22pf c417 0.1f c416 0.1f c414 0.1f r417 10k ? c421 22pf c419 0.1f c422 0.1f inh2 inh1 avdd_5v avdd_5v c426 10f c413 10f optional vga drive circuit for channels a and b c409 0.1f r411 10k ? r412 10k ? dnp c403 dnp l404 0 ? r403 dnp l408 0 ? 24 17 20 23 18 22 19 21 r404 dnp l406 0 ? l405 0 ? l402 0 ? l403 0 ? l407 0 ? c408 0.1f c407 0.1f c406 0.1f c405 0.1f r410 187 ? r409 187 ? r408 187 ? r407 187 ? c402 dnp l401 0 ? c401 dnp r405 374 ? r406 374 ? ch_a ch_b ch_b ch_a avdd_5v avdd_5v avdd_5v c404 dnp r401 dnp r402 dnp 31 10 26 25 14 27 3 6 4 5 1 8 32 9 15 16 vg 28 13 29 12 30 11 2 7 com1 com2 enbl enbv gain hilo inh1 inh2 lmd1 lmd2 lon1 lon2 lop1 lop2 mode nc rclmp vcm1 vcm2 vin1 vin2 vip1 vip2 voh1 voh2 vol1 vol2 vps1 vps2 vpsv ad8332 u401 comm comm r413 10k ? dnp r424 10k ? dnp c412 0.1f c411 1000pf rclamp pin hilo pin = lo = 50mv hilo pin = h = 75mv 05727-018 power down enable (0?1v = disable power) r416 274 ? populate l401-l408 with 0 ? resistors or design your own filter. y1 vcc y2 a2 gnd a1 spi circuitry from fifo sdio_odm avdd_dut r431 1k ? r432 1k ? r433 1k ? avdd_3.3v 1 2 34 5 6 nc7wz07 u403 r425 10k ? avdd_dut reset/reprogram 1 2 3 4 s401 +3.3v = normal operation = avdd_3.3v +5v = programming = avdd_5v avdd_5v avdd_3.3v j402 c427 0.1f r418 4.75k ? pic12f629 r419 261 ? 4 3 1 2 5 6 8 7 u402 cr401 gp0 gp1 gp2 gp4 gp5 vdd vss mclr/ gp3 remove when using or programming pic (u402) r427 0 ? r420 0 ? r428 0 ? r426 0 ? sdo_cha sdi_cha sclk_cha csb1_cha c429 0.1f sclk_dtp csb_dut avdd_dut y1 vcc y2 a2 gnd a1 1 2 34 5 6 u404 r430 10k ? r429 10k ? nc7wz16 c428 0.1f pic programming header mclr/gp3 gp0 gp1 picvcc mclr/gp3 gp0 gp1 picvcc 9 7 5 3 1 10 8 6 4 2 j401 e401 r421 0-dnp r423 0-dnp r422 0-dnp optional dnp: do not populate figure 75. evaluation board schematic, optional du t analog input drive and spi interface (continued)
ad9228 rev. 0 | page 42 of 52 mounting holes connected to ground h2 h3 h1 h4 p1 p2 p3 p4 p5 p6 p7 p8 optional power input +5.0v +1.8v +1.8v +3.3v 1 2 3 4 5 6 7 8 p501 3.3v_avdd 5v_avdd l502 10h dut_avdd dut_drvdd c509 0.1f c508 10f l503 10h l501 10h drvdd_dut avdd_dut 0.1f c505 0.1f c507 c503 0.1f avdd_5v 10f c504 c502 10f 10f c506 avdd_3.3v 10h l508 decoupling capacitors avdd_3.3v 0.1f c524 0.1f c525 c521 0.1f c531 0.1f c530 0.1f c529 0.1f c522 0.1f c528 0.1f c527 0.1f c526 0.1f 0.1f c517 0.1f c516 c518 0.1f c520 0.1f c519 0.1f c523 0.1f drvdd_dut avdd_dut avdd_5v smdc110f power supply input 6v, 2v maximum 1 3 2 p503 c501 10f f501 d502 3a shot_rect do-214ab d501 s2a_rect 2a do-214aa 2 1 3 4 fer501 choke_coil cr501 r501 261 ? pwr_in + gnd input output1 gnd input output1 output4 output4 gnd input gnd input dnp: do not populate 4 2 3 1 adp33339akc-5 u504 4 2 3 1 adp33339akc-3.3 u502 1 32 4 u501 adp33339akc-1.8 1 32 4 u503 adp33339akc-1.8 l505 10h 10h l504 c515 1f c513 1f c512 1f c514 1f pwr_in pwr_in dut_avdd dut_drvdd 5v_avdd 3.3v_avdd pwr_in pwr_in c532 1f c534 1f c535 1f c533 1f l507 10h l506 10h output1 output1 output4 output4 05727-019 figure 76. evaluation board sc hematic, power supply inputs
ad9228 rev. 0 | page 43 of 52 05727-020 figure 77. evaluation board layout, primary side
ad9228 rev. 0 | page 44 of 52 0 5727-021 figure 78. evaluation board layout, ground plane
ad9228 rev. 0 | page 45 of 52 05727-022 figure 79. evaluation board layout, power plane
ad9228 rev. 0 | page 46 of 52 05727-023 figure 80. evaluation board layout, secondary side (mirrored image)
ad9228 rev. 0 | page 47 of 52 table 16. evaluation board bill of materials (bom) item qnty. per board refdes device pkg. value mfg. mfg. part number 1 1 ad9228lfcsp_reva pcb pcb pcb 2 75 c101, c102, c107, c108, c109, c114, c115, c116, c121, c122, c123, c128, c201, c203, c204, c205, c206, c210, c211, c212, c213, c216, c217, c218, c219, c220, c221, c222, c223, c224, c310, c311, c312, c313, c314, c316, c319, c320, c321, c324, c325, c409, c410, c412, c414, c416, c417, c419, c422, c423, c424, c425, c427, c428, c429, c503, c505, c507, c509, c516, c517, c518, c519, c520, c521, c522, c523, c524, c525, c526, c527, c528, c529, c530, c531 capacitor 402 0.1 f, ceramic, x5r, 10 v, 10% tol panasonic ecj-0eb1a104k 3 4 c104, c111, c118, c125 capacitor 402 2.2 pf, ceramic, cog, 0.25 pf tol, 50 v murata grm1555c1h2r2gz01b 4 4 c315, c326, c413, c426 capacitor 805 10 f, 6.3 v 10% ceramic, x5r avx 08056d106kat2a 5 1 c202 capacitor 603 2.2 f, ceramic, x5r, 6.3 v, 10% tol panasonic ecj-1vb0j225k 6 2 c309, c411 capacitor 402 1000 pf, ceramic, x7r, 25 v, 10% tol kemet c0402c102k3ractu 7 4 c317, c322, c415, c420 capacitor 402 0.018 f, ceramic, x7r, 16 v, 10% tol avx 0402yc183kat2a 8 4 c318, c323, c418, c421 capacitor 402 22 pf, ceramic, npo, 5% tol, 50 v kemet c0402c220j5gactu 9 1 c501 capacitor 1206 10 f, tantalum, 16 v, 20% tol rohm tca1c106m8r 10 9 c214, c512, c513, c514, c515, c532, c533, c534, c535 capacitor 603 1 f, ceramic, x5r, 6.3 v, 10% tol panasonic ecj-1vb0j105k 11 8 c305, c306, c307, c308, c405, c406, c407, c408 capacitor 805 0.1 f, ceramic, x7r, 50 v, 10% tol avx 08055c104kat2a 12 4 c502, c504, c506, c508 capacitor 603 10 f, ceramic, x5r, 6.3 v, 20% tol panasonic ecj-1vb0j106m 13 1 cr201 diode sot-23 30 v, 20 ma, dual schottky agilent technologies hsms2812 14 2 cr401, cr501 led 603 green, 4 v, 5 m candela panasonic lnj306g8tra 15 1 d502 diode do-214ab 3 a, 30 v, smc micro commercial co. sk33msct 16 1 d501 diode do-214aa 2 a, 50 v, smc micro commercial co. s2a
ad9228 rev. 0 | page 48 of 52 item qnty. per board refdes device pkg. value mfg. mfg. part number 17 1 f501 fuse 1210 6.0 v, 2.2 a trip- current resettable fuse tyco/raychem nanosmdc110f-2 18 1 fer501 choke coil 2020 10 h, 5 a, 50 v, 190 @ 100 mhz murata dlw5bsn191sq2l 19 12 fb101, fb102, fb103, fb104, fb105, fb106, fb107, fb108, fb109, fb110, fb111, fb112 ferrite bead 603 10 , test freq 100 mhz, 25% tol, 500 ma murata blm18ba100sn1 20 1 jp301 connector 2-pin 100 mil header jumper, 2-pin samtec tsw-102-07-g-s 21 2 j205, j402 connector 3-pin 100 mil header jumper, 3-pin samtec tsw-103-07-g-s 22 1 j201 to j204 connector 12-pin 100 mil header male, 4 3 triple row straight samtec tsw-104-08-g-t 23 1 j401 connector 10-pin 100 mil header, male, 2 5 double row straight samtec tsw-105-08-g-d 24 8 l501, l502, l503, l504, l505, l506, l507, l508 ferrite bead 1210 10 h, bead core 3.2 2.5 1.6 smd, 2 a panasonic-ecg exc-cl3225u1 25 4 l309, l310, l409, l410 inductor 402 120 nh, test freq 100 mhz, 5% tol, 150 ma murata lqg15hnr12j02b 26 16 l301, l302, l303, l304, l305, l306, l307, l308, l401, l402, l403, l404, l405, l406, l407, l408 resistor 805 0 , 1/8 w, 5% tol panasonic erj-6gey0r00v 27 1 osc201 oscillator smt clock oscillator, 65.00 mhz, 3.3 v cts reeves cb3lv-3c-65m0000-t 28 5 p101, p103, p105, p107, p201 connector sma side-mount sma for 0.063" board thickness johnson components 142-0711-821 29 1 p202 connector header 1469169-1, right angle 2-pair, 25 mm, header assembly tyco 1469169-1 30 1 p503 connector 0.1", pcmt rapc722, power supply connector switchcraft sc1153 31 15 r201, r205, r214, r215, r221, r239, r312, r315, r318, r411, r414, r417, r425, r429, r430 resistor 402 10 k, 1/16 w, 5% tol panasonic erj-2gej103x 32 14 r103, r117, r129, r142, r216, r217, r218, r223, r224, r237, r420, r426, r427, r428 resistor 402 0 , 1/16 w, 5% tol panasonic erj-2ge0r00x 33 4 r102, r115, r128, r141 resistor 402 64.9 , 1/16 w, 1% tol panasonic erj-2rkf64r9x 34 4 r104, r116, r130, r143 resistor 603 0 , 1/10 w, 5% tol panasonic erj-3gey0r00v
ad9228 rev. 0 | page 49 of 52 item qnty. per board refdes device pkg. value mfg. mfg. part number 35 15 r109, r111, r112, r123, r125, r126, r135, r138, r139, r148, r149, r150, r431, r432, r433 resistor 402 1 k, 1/16 w, 1% tol panasonic erj-2rkf1001x 36 8 r108, r110, r121, r122, r134, r136, r146, r147 resistor 402 33 , 1/16 w, 5% tol panasonic erj-2gej330x 37 4 r161, r162, r163, r164 resistor 402 499 , 1/16 w, 1% tol panasonic erj-2rkf4990x 38 3 r202, r203, r204 resistor 402 100 k, 1/16 w, 1% tol panasonic erj-2rkf1003x 39 1 r222 resistor 402 4.02 k, 1/16 w, 1% tol panasonic erj-2rkf4021x 40 1 r213 resistor 402 49.9 , 1/16 w, 0.5% tol susumu rr0510r-49r9-d 41 1 r229 resistor 402 4.99 k, 1/16 w, 5% tol panasonic erj-2rkf4991x 42 2 r230, r319 potentiometer 3-lead 10 k, cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 w bc components ct-94w-103 43 1 r228 resistor 402 470 k, 1/16 w, 5% tol yageo america 9c04021a4703jlhf3 44 1 r320 resistor 402 39 k, 1/16 w, 5% tol susumu rr0510p-393-d 45 8 r307, r308, r309, r310, r407, r408, r409, r410 resistor 402 187 , 1/16 w, 1% tol panasonic erj-2rkf1870x 46 4 r305, r306, r405, r406 resistor 402 374 , 1/16 w, 1% tol panasonic erj-2rkf3740x 47 4 r316, r317, r415, r416 resistor 402 274 , 1/16 w, 1% tol panasonic erj-2rkf2740x 48 11 r245, r247, r249, r251, r253, r255, r257, r259, r261, r263, r265 resistor 201 0 , 1/20 w, 5% tol panasonic erj-1ge0r00c 49 4 r418 resistor 402 4.75 k, 1/16 w, 1% tol panasonic erj-2rkf4751x 50 1 r419 resistor 402 261 , 1/16 w, 1% tol panasonic erj-2rkf2610x 51 1 r501 resistor 603 261 , 1/16 w, 1% tol panasonic erj-3ekf2610v 52 2 r240, r241 resistor 402 243 , 1/16 w, 1% tol panasonic erj-2rkf2430x 53 2 r242, r243 resistor 402 100 , 1/16 w, 1% tol panasonic erj-2rkf1000x 54 1 s401 switch smd light touch, 100ge, 5 mm panasonic evq-plda15 55 5 t101, t102, t103, t104, t201 transformer cd542 adt1-1wt, 1:1 impedance ratio transformer mini-circuits adt1-1wt 56 2 u501, u503 ic sot-223 adp33339akc-1.8, 1.5 a, 1.8 v ldo regulator adi adp33339akc-1.8
ad9228 rev. 0 | page 50 of 52 item qnty. per board refdes device pkg. value mfg. mfg. part number 57 2 u301, u401 ic lfcsp, cp-32 ad8332acp, ultralow noise precision dual vga adi ad8332acp 58 1 u504 ic sot-223 adp33339akc-5 adi adp33339akc-5 59 1 u502 ic sot-223 adp33339akc-3.3 adi adp33339akc-3.3 60 1 u201 ic lfcsp, cp-48-1 ad9228-65, quad, 12-bit, 65 msps serial lvds 1.8 v adc adi ad9228bcpz-65 61 1 u203 ic sot-23 adr510ar, 1.0 v, precision low noise shunt voltage reference adi adr510ar 62 1 u202 ic lfcsp cp-32-2 ad9515 adi ad9515bcpz 63 1 u403 ic sc70, maa06a nc7wz07 fairchild nc7wz07p6x 64 1 u404 ic sc70, maa06a nc7wz16 fairchild nc7wz16p6x 65 1 u402 ic 8-soic flash prog mem 1kx14, ram size 64 8, 20 mhz speed, pic12f controller series microchip pic12f629-i/sn
ad9228 rev. 0 | page 51 of 52 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 81. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9228bcpz-40 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 ad9228bcpzrl-40 1 ?40c to +85c 48-lead lead frame chip scal e package [lfcsp_vq] tape and reel cp-48-1 ad9228bcpz-65 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 ad9228bcpzrl-65 1 ?40c to +85c 48-lead lead frame chip scal e package [lfcsp_vq] tape and reel cp-48-1 AD9228-65EB evaluation board 1 z = pb-free part.
ad9228 rev. 0 | page 52 of 52 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05727C0C4/06(0)

▲Up To Search▲

Price & Availability of AD9228-65EB

	To Download AD9228-65EB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .